1. Technical Field
Various embodiments of the present invention relate to a semiconductor memory apparatuses. In particular, certain embodiments relate to a 3D (three-dimensional) semiconductor apparatus having a plurality of stacked chips.
2. Related Art
In order to increase the degree of integration of a semiconductor apparatus, there has been developed a three-dimensional semiconductor apparatus with a plurality of stacked and packaged chips. Since two or more chips are vertically stacked, the 3D semiconductor apparatus can achieve a higher degree of integration in an equivalent space.
Various schemes exist to realize the three-dimensional semiconductor apparatus. In one of such schemes, a plurality of chips with an identical structure are stacked and the stacked chips are coupled to one another using wires such as metal lines, so that they operate as a single semiconductor apparatus.
Also, recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed in the art, in which silicon vias are formed through a plurality of stacked chips so that all the chips are electrically connected to one another. Since the chips are electrically connected to one another through the silicon vias vertically passing through the chips in the TSV type semiconductor apparatus, it is possible to efficiently reduce the area of a package, as compared with a semiconductor apparatus in which respective chips are electrically connected to one another through bonding wirings placed at the edges around the chips.
The number of TSVs for connecting the plurality of chips tends to increase in proportion to the degree of integration of the semiconductor apparatus. Therefore, along with the increase in the number of TSVs, a technology for replacing failed TSVs with normal TSVs is needed. This can be accomplished using fuse information, for example, a fuse circuit for storing information as to whether TSVs are normal or failed. The fuse circuit disposed in each of the stacked chips might help to solve a problem which is likely to occur in association with the replacement of TSVs, but such circuit configuration may lead to inefficiency for securing a chip area.